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Articles by P. Sakthivel
Total Records ( 5 ) for P. Sakthivel
  Sathyabalan P. , V. Selladurai and P. Sakthivel
  Problem statement: The reinforcements added to an alloy lead to variation in properties. The content and size of the reinforcement influences the properties of composites. Very little research has been carried out in hybrid composites. Work on hybrid LM6 aluminium alloy metal matrix composites (MMC) with flyash and SiC has been initiated here. The effect of the four parameters, size and weight of the reinforcements on the hardness and wear loss has been studied. Approach: Artificial neural networks, from the artificial intelligence family, is a type of information processing system, based on modeling the neural system of human brain. The effect of the parameters was investigated using ANN. Central composite rotatable method of design of experiments was used to arrive at the combination and the number of specimens. The specimens were prepared using the liquid metallurgy route and tested. Pin-on-disc apparatus was used for determining wear. Rockwell hardness on C scale was determined. The data from the experiments were used for training and testing the network. Results: The accuracy in ANN prediction was appreciable with the error estimated for wear loss and hardness being less than 2%. Conclusions/Recommendations: The ANN prediction is quick and economical way of estimating the properties.
  T. Kalavathidevi and P. Sakthivel
  This study addresses a systematic unfolding transformation technique to transform the conventional viterbi architecture to equivalent digit serial. The originality of the unfolding technique lies in the generation of functionally correct control circuits in digit serial architectures. Convolutional code is an essential Forward Error Correcting (FEC) code for many wireless communication systems. Viterbi decoder is an optimal algorithm for decoding a convolution code. Power dissipation is recognized as a critical parameter in modern Very Large Scale Integrated circuit (VLSI) design field. Viterbi decoder employed in digital wireless communication is complex and dissipates large power. The aim of the proposed method is to obtain high speed and low power Viterbi decoder using bit-level pipelined digit-serial architecture for various digit size and word length. In the digit-serial architecture N bits are processed per clock cycle and a word is processed per W/N clock cycles (W: word length, N: digit size). Bit-level pipelining technique is applied for each bit as well as for each block. Digit serial architecture and bit-level pipelining achieves high speed and low power. With this technique the viterbi decoder is designed for word length W = 8, 16, 32 and digit size N = 2, 4. The functionality is simulated and synthesized using Xilinx ISE 13.2i.
  S. Lokesh , O. UMA Maheswari and P. Sakthivel
  As technology processes scale up and design complexities grow, system-on-chip integration continues to rise rapidly. According to these trends, increasing test data volume is one of the biggest challenges in the testing industry. In this study, we propose a test data compression based Three State Skip (TSS) Logic for Low Power Built in Self Test (BIST) applications. The Three State Skip (TSS) primarily aims at reducing the switching activity during a scan by skipping preselected test vectors. For improving the compression efficiency, a Reconfigurable Johnson Counter (RJC) is used to reconfigure and skip function. It is useful to reuse previously used data for making present data by using the function of feedback or tapping of the Linear Feedback Shift Register (LFSR). Three State Skip circuit is developed to achieve little scan power by splitting and skipping long scan chain switching activities. This research solves the challenges faced in Fault detection circuits with the proposed Three State Skip logic. The Efficiency of such system is compared with Two Folded State Skip (TFSS) Logic and generates minimum test patterns by skipping the scan chain.
  A. Akilandeswari and P. Sakthivel
  Now a days, there is very much use of multimedia technologies, so there is need of improvement in the image compression technique in terms of performance and also the new features. Due to advantages of the discrete wavelet transform over the traditional transforms, it became very popular in the area of image processing. A Fast Architecture (FA) for 2-D Discrete Wavelet Transform (DWT) with use of improved Lifting scheme is presented in this study. Likewise embedded decimation technique used for the 1-D Discrete Wavelet Transform (DWT), pipelined and parallel structured 2-D DWT proposed in this study. In this study, we have proposed the multiplier less pipeline method for DWT. The advantage of this technique is that it does maximum utilization of the designed hardware. It does the J levels of decomposition when input image of size NxN given in an around 2N2 (1-4raise to-j)/3 of clock cycles. This method is called as Fast Architecture (FA). Using this technique throughput rate, output latency, etc are improved at the cost of some additional hardware. So, proposed architecture is better alternative for high speed applications.
  P. Sakthivel , R. Delhi Babu and P. Narayanasamy
  Problem statement: This study presented the optimized test scheduling and test access for ITC-02 SOC benchmark circuits using genetic algorithm. In the scheduling procedure of SOC, scheduling problem was formulated as a sequence of two problems and solved. Approach: Test access mechanism width was partitioned into two and three partitions and the applications of test vectors and test vector assignments for different partitions were scheduled using different operators of genetic algorithm. Results: The test application time was calculated in terms of CPU time cycles for two and three partitions of twelve ITC-02 SOC benchmark circuits and the results were compared with the integer linear programming approach. Conclusion: The results showed that the genetic algorithm based approach gives better results.
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