Wei Lin
College of Physics and Information Engineering of Fuzhou University, Fuzhou, Fujian, China
Shi-Zhen Huang
Fujian Key Laboratory of Microelectronics and Integrated Circuits
Wen-Long Shi
Fujian Key Laboratory of Microelectronics and Integrated Circuits
ABSTRACT
As circuit sizes grow ever larger, test data volume and test application time grow unwieldy even in the very efficient scan based designs. Adaptive scan architecture of Design for Test (DFT) technique is used to reduce test application time and test data volume. In our research, we analyze the technique of the scan test architecture. Based on the analysis, the adaptive scan of DFT technique is succeeding applied to a SOC chip. Experimental results show that the test cost of the SOC chip is greatly reduced. Compared with the original program, the fault coverage is reached 97%, the test data volume is decreased 8.79 times, the test time is reduced almost 6 times.
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How to cite this article
Wei Lin, Shi-Zhen Huang and Wen-Long Shi, 2013. A Case Study on the Scan Architecture of DFT Technique. Information Technology Journal, 12: 6933-6939.
DOI: 10.3923/itj.2013.6933.6939
URL: https://scialert.net/abstract/?doi=itj.2013.6933.6939
DOI: 10.3923/itj.2013.6933.6939
URL: https://scialert.net/abstract/?doi=itj.2013.6933.6939
REFERENCES
- Alampally, S., J. Abraham, R.A. Parekhji, R. Kapur and T.W. Williams, 2008. Evaluation of entropy driven compression bounds on industrial designs. Proceedings of the 17th IEEE Asian Test Symposium, November 13-18, 2008, Sapporo, Japan, pp: 13-18.
CrossRef - Arslan, B. and A. Orailoglu, 2004. Circularscan: A scan architecture for test cost reduction. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Volume 2, Febuary 16-20, 2004, Paris, France, pp: 1290-1295.
CrossRef - Chandra, A., R. Kapur and Y. Kanzawa, 2009. Scalable adaptive scan (SAS). Proceedings of the Conference on Design, Automation and Test in Europe, April 20-24, 2009, Nice, France, pp: 1476-1481.
CrossRef - Devanathan, V.R., C.P. Ravikumar and V. Kamakoti, 2007. Reducing SoC test time and test power in hierarchical scan test: Scan architecture and algorithms. Proceedings of the 20th International Conference on VLSI Design and 6th International Conference on Embedded Systems, January 6-10, 2007, Bangalore, pp: 351-356.
CrossRef - Wang, L.T., X.Q. Wen, H. Furukawa, F.S. Hsu and S.H. Lin et al., 2004. VirtualScan: A new compressed scan technology for test cost reduction. Proceedings of the IEEE International Test Conference, October 26-28, 2004, Charlotte, NC, USA., pp: 916-925.
CrossRef - Hamzaoglu, I. and J.H. Patel, 2000. Reducing test application time for built-in-self-test test pattern generators. Proceedings of the 18th IEEE VLSI Test Symposium, April 30-May 4, 2000, Montreal, Que., pp: 369-375.
CrossRef - Mullane, B., M. Higgins and C. MacNamee, 2008. IEEE 1500 core wrapper optimization techniques and implementation. Proceedings of the IEEE International Test Conference, October 28-30, 2008, Santa Clara, CA., pp: 1-10.
CrossRef - Hsu, F.F., K.M. Butler and J.H. Patel, 2001. A case study on the implementation of the Illinois scan architecture. Proceedings of the IEEE International Test Conference, October 30-November 1, 2001, Baltimore, MD., pp: 538-547.
CrossRef - Iyengar, V. and A. Chandra, 2003. A unified SOC test approach based on test data compression and TAM design. Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 3-5, 2003, Boston, MA, USA., pp: 511-518.
CrossRef - Kapur, R., S. Mitra and T.W. Williams, 2008. Historical perspective on scan compression. IEEE Design Test Comput., 25: 114-120.
CrossRef - Kim, K.S. and M. Zhang, 2008. Hierarchical test compression for SoC designs. IEEE Design Test Comput., 25: 142-148.
CrossRef - Lingappan, L., S. Ravi, A. Raghunathan, N.K. Jha and S.T. Chakradhar, 2006. Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques. IEEE Trans. Comput. Aided Design Integrated Circuits Syst., 25: 2193-2206.
CrossRef - Mrugalski, G., N. Mukherjee, J. Rajski, D. Czysz and J. Tyszer, 2009. Compression based on deterministic vector clustering of incompatible test cubes. Proceedings of the IEEE International Test Conference, November 1-6, 2009, Austin, TX., pp: 1-10.
CrossRef - Nadeau-Dostie, B., S.M.I. Adham and R. Abbott, 2009. Improved core isolation and access for hierarchical embedded test. IEEE Design Test Comput., 26: 18-25.
CrossRef - Gonciari, P.T., B.M. Al-Hashimi and N. Nicolici, 2002. Improving Compression ratio, area overhead and test application time for system-on-a-chip test data compression/decompression. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, March 4-8, 2002, Paris, pp: 604-611.
CrossRef - Rao, W., A. Orailoglu and G. Su, 2004. Frugal linear network-based test decompression for drastic test cost reductions. Proceedings of the International Conference on Computer-Aided Design, November 7-11, 2004, San Jose, California, pp: 721-725.
CrossRef - Srinivasan, P. and R. Farrell, 2010. Hierarchical DFT with combinational scan compression, partition chain and RPCT. Proceedings of the IEEE Annual Symposium on VLSI, July 5-7, 2010, Lixouri, Kefalonia, pp: 52-57.
CrossRef - Ziaja, T. and M. Gala, 2008. Overview of DFT features of the sun microsystems niagara2 CMP/CMT SPARC chip. Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, June 2-4, 2008, Austin, TX., pp: 151-154.
CrossRef