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Reddy, N.S.S., 2011. Minimization of power dissipation in 16 bit processor using low power tecniques. Asian J. Applied Sci., 4: 657-662. CrossRefDirect Link |
Citation to this article as recorded by
Evolutionary Approach of Adiabatic Logic Design on Low Power
Solution �A Robust Survey i-manager`s Journal on Communication Engineering and Systems Vol. 1, Issue 2, 36, 2012 |
Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques Asian Journal of Applied Sciences Vol. 4, Issue 6, 657, 2011 |
How to cite this article
P. Vijayakumar, M. Shanthanalakshmi and K. Gunavathi, 2007. Optimizing CMOS Circuits for Performance Improvements Using Adiabatic Logic. Information Technology Journal, 6: 325-331.
DOI: 10.3923/itj.2007.325.331
URL: https://scialert.net/abstract/?doi=itj.2007.325.331
DOI: 10.3923/itj.2007.325.331
URL: https://scialert.net/abstract/?doi=itj.2007.325.331