Information Technology Journal1812-56381812-5646Asian Network for Scientific Information10.3923/itj.2011.2161.2167HuJianping YuXiaoying ChenJindan 1120111011With the growing uses of portable computers, energy-efficient designs have become more and more important for computer hardware. This study presents new low leakage power flip-flops with power-gating scheme for ultra-low power systems. The proposed flip-flops are realized based on CMOS ratioed latches with the master-slave structure. Dual-threshold CMOS (DTCMOS) and channel length biasing techniques are used for the flip-flops with power-gating scheme to reduce leakage power dissipations. All circuits are verified with HSPICE simulations by using the BSIM4 predictive models at a 45 nm CMOS process. The results showed that the proposed low leakage ratioed flip-flop realized with the integrated leakage reduction techniques achieves large leakage savings compared with the transmission-gate flip-flop.]]>Kim, N.S., T. Austin, D. Baauw, T. Mudge and K. Flautner et al.,2003366875Rabaey, J.M.,1996Roy, K., S. Mukhopadhyay and H. Mahmoodi-Meimand,200391305327Fallah, F. and M. Pedram,200588509519Kao, J. and A. Chandrakasan,20012001pp: 317320Seomun, J., J. Kim and Y. Shin,20072007pp: 103106Zhang, W., L. Su, Y. Zhang, L. Li and J. Hu,201120147162Gupta, P., A.B. Kahng, P. Sharma and D. Sylvester,20062514751485Zhao, W. and Y. Cao,20065328162823