Information Technology Journal1812-56381812-5646Asian Network for Scientific Information10.3923/itj.2012.1442.1448GuFei LingChunqing KuangJishun ZhouYingbo 1020121110In this study, structure of fault tolerance adder based on
Radix 2 Signed Digital (SD) representation is proposed. The carry-free
property of the SD adder that faults impact limited to a few digits can be used
to fault detection which is based on parity checking assumed single fault set.
Using an encoding scheme to get the parity value of digits involved in computing,
this parity values can be exploited to check the circuit. An error information
register is set to store the checking results and the bits of the register indicate
the corresponding units faulty or not. According to the fault type, recomputation
or reconfiguration is used to error correction. The hardware overhead appending
Fault-Tolerant is about 120% and the maximum combinational path delay of the
proposed adder is constant with the increase of operands.]]>Yu, F.X., J.R. Liu, Z.L. Huang, H. Luo and Z.M. Lu,2010610681080Johnson, J., W. Howes, M. Wirthlin, D.L. McMurtrey, M. Caffrey, P. Graham and K. Morgan,20082008pp: 111D'Angelo, S., C. Metra and G. Sechi,19991999pp: 330338Hamidi, H., A. Vafaei and A.H. Monadjemi,2009939473956Ziabari, M., A.M. Kassai, A. Ziabari and S.E. Maklavani,2008825692576Hosseinzadeh, M. and K. Navi,2007737293735Kharbash, F., and G.M. Chaudhry,20072007pp: 14Morozov, A., V.V. Saposhnikov, V.V. Saposhnikov and M. Gossel,20002000pp: 141146Townsend, W.J., J.A. Abraham and E.E. Swartzlander Jr.,20032003pp: 250256Piuri, V. and E.E. Swartzlander, Jr.,19991999pp: 265273Barati, A., M. Dehghan, A. Movaghar and H. Barati,2008832733278Avizienis, A.,1961EC-10389400Cardarilli, G.C., M. Ottavi, S. Pontarelli, M. Re and A. Salsano,200655534540Alavi, S.R. and K. Faez,20072007pp: 214218Yilmaz, M., D.R. Hower and S. Ozev,20062006pp: 110