Xiang Xue-Cheng
Faculty of Information Science and Technology, Ningbo University, Ningbo City, Zhejiang, 315211, China
Hu Jian-Ping
Faculty of Information Science and Technology, Ningbo University, Ningbo City, Zhejiang, 315211, China
ABSTRACT
In this study, standard cells based on single-rail MOS Current Mode Logic (SRMCML) for highspeed applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries which include basic logic gates such as inverter, NAND, NOR. The main design parameters including bias current, output voltage swing and device sizes of transistors in SRMCML cells are optimized to minimize Power Delay Product (PDP). The optimizations and designs for basic standard cells based on SRMCML are carried out. A full adder is verified with the proposed standard cells by using commercial EDA tools. Compared with the conventional static CMOS, the power delay product of the SRMCML AND and OR cells provide a reduction of 50.27 and 63.06% at 3 GHz, respectively. The results indicate the proposed SRMCML standard cells are a good choose in high-speed digital applications.
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How to cite this article
Xiang Xue-Cheng and Hu Jian-Ping, 2013. Single-Rail MCML Standard Cells for High-Speed Digital Systems. Information Technology Journal, 12: 4999-5004.
DOI: 10.3923/itj.2013.4999.5004
URL: https://scialert.net/abstract/?doi=itj.2013.4999.5004
DOI: 10.3923/itj.2013.4999.5004
URL: https://scialert.net/abstract/?doi=itj.2013.4999.5004
REFERENCES
- Cevrero, A., F. Regazzoni, M. Schwander, S. Badel, P. Ienne and Y. Leblebici, 2011. Power-gated MOS current mode logic (PG-MCML): A power aware DPA-resistant standard cell library. Proceedings of the 48th ACM/IEEE Design Automation Conference, June 5-9, 2011, New York, pp: 1014-1019.
Direct Link - Badel, S., I. Hatirnaz and Y. Leblebici, 2005. SEMI-Automated design of a MOS current-mode logic standard cell library from generic components. Res. Microelectronics Electronics, 2: 355-358.
Direct Link - Somasekhar, D. and K. Roy, 1998. LVDCSL: A high fan-in, high performance, low-voltage differential current switch logic family. IEEE Trans. Very Large Scale Integration Syst., 6: 573-577.
CrossRef - Kim, J.B., 2009. Low-power MCML circuit with sleep-transistor. Proceeding of the 8th IEEE International Conference on ASIC, October 20-23, 2009, Changsha, Hunan, pp: 25-28.
CrossRef - Alioto, M. and G. Palumbo, 2003. Design strategies for source coupled logic gates. IEEE Trans. Circuits Syst. I: Fundamental Theory Appl., 50: 640-654.
CrossRef - Tanabe, A., M. Umetani, I. Fujiwara, T. Ogura and K. Kataoka et al., 2001. 0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid State Circuits, 36: 988-996.
CrossRefDirect Link