Zhang Ying
College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, Jiangsu, China
Wu Ning
College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, Jiangsu, China
Ge Fen
College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, Jiangsu, China
Chen Xin
College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, Jiangsu, China
ABSTRACT
A novel design of a core test wrapper for NoC-based SoC is proposed in this study and the wrapper is adaptive to unicast and multicast testing. A test response comparator is particularly added to the wrapper and it improves testing efficiency and supports various test modes. Moreover, the additional parallel bypass circuit further optimizes the design. A 2D Mesh NoC was constructed with these wrapped IP cores and implemented unicast and multicast testing. The experimental results show that the wrapper can effectively realize embedded IP test access and isolation and has the good adaptability to support various NoC test strategies.
PDF References Citation
How to cite this article
Zhang Ying, Wu Ning, Ge Fen and Chen Xin, 2013. Core Test Wrapper Design for Unicast and Multicast NOC Testing. Information Technology Journal, 12: 8242-8248.
DOI: 10.3923/itj.2013.8242.8248
URL: https://scialert.net/abstract/?doi=itj.2013.8242.8248
DOI: 10.3923/itj.2013.8242.8248
URL: https://scialert.net/abstract/?doi=itj.2013.8242.8248
REFERENCES
- Aghaei, B. and S. Babaei, 2009. The new test wrapper design for core testing in packet-switched micro-network on chip. Proceedings of the 2nd International Conference on Power Electronics and Intelligent Transportation System, Volume 2, December 19-20, 2009, Shenzhen, China, pp: 346-352.
CrossRef - Amory, A.M., K. Goossens, E.J. Marinissen, M. Lubaszewski and F. Moraes, 2007. Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput. Digital Tech., 1: 197-206.
Direct Link - Benini, L. and G. De Micheli, 2002. Networks on chips: A new SoC paradigm. IEEE Comput., 35: 70-78.
CrossRef - Ciordas, C., T. Basten, A. Radulescu, K. Goossens and J.V. Meerbergen, 2005. An event-based monitoring service for networks on chip. ACM Trans. Design Autom. Electron. Syst., 10: 702-723.
CrossRefDirect Link - Hussin, F.A., T. Yoneda and H. Fujiwara, 2007. Optimization of NoC wrapper design under bandwidth and test time constraints. Proceedings of the 12th IEEE European Test Symposium, May 20-24, 2007, Freiburg, Germany, pp: 35-42.
CrossRef - Hussin, F.A., T. Yoneda and H. Fujiwara, 2008. On NoC bandwidth sharing for the optimization of area cost and test application time. IEICE Trans. Inform. Syst., 91: 1999-2007.
Direct Link - Nourmandi-Pour, R., N. Mousavian and A. Khadem-Zadeh, 2011. BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards. Microelectron. J., 42: 667-680.
CrossRefDirect Link