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Elamaran, V., G. Rajkumar, S.S. Rajpurohit and R.A. Krishnan, 2014. A novel low power adder-subtractor using efficient XOR gates. J. Applied Sci., 14: 1623-1627. CrossRefDirect Link |
Rajesh, K.S.S.K., S.H.H. Subramani and V. Elamaran, 2014. CMOS VLSI design of low power comparator logic circuits. Asian J. Sci. Res., 7: 238-247. CrossRefDirect Link |
Subramani, S.H.H., K.S.S.K. Rajesh and V. Elamaran, 2014. Low energy, low power adder logic cells: A CMOS VLSI implementation. Asian J. Sci. Res., 7: 248-255. CrossRefDirect Link |
V. Elamaran, N. Raju , Anooj Krishnan , Kalagarla Abhiram 2014. CMOS VLSI Implementation of Adders with Low Leakage Power J. Applied Sci., 14: 1550-1556. CrossRef |
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TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE
STUDY Journal of Circuits, Systems and Computers Vol. 23, Issue 05, 1450061, 2014 |
How to cite this article
Jianping Hu, Xiaoying Yu and Jindan Chen, 2011. New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems. Information Technology Journal, 10: 2161-2167.
DOI: 10.3923/itj.2011.2161.2167
URL: https://scialert.net/abstract/?doi=itj.2011.2161.2167
DOI: 10.3923/itj.2011.2161.2167
URL: https://scialert.net/abstract/?doi=itj.2011.2161.2167